The present invention relates to the programming of nonvolatile programmable semiconductor memory, and more particularly, to programming nonvolatile programmable semiconductor memory cells that use a breakdown phenomena in a dielectric, such as a MOS gate dielectric to store digital information.
Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. One commonly available type of nonvolatile memory is the programmable read-only memory (xe2x80x9cPROMxe2x80x9d), which uses word line-bit line crosspoint elements such as fuses, anti-fuses, and trapped charge devices such as the floating gate avalanche injection metal oxide semiconductor (xe2x80x9cFAMOSxe2x80x9d) transistor to store logical information. PROM typically is not reprogrammable.
An example of one type of PROM cell that uses the breakdown of a silicon dioxide layer in a capacitor to store digital data is disclosed in U.S. Pat. No. 6,215,140 to Reisinger et al. The basic PROM disclosed by Reisinger et al. uses a series combination of an oxide capacitor and a junction diode as the crosspoint element. An intact capacitor represents the logic value 0, and an electrically broken-down capacitor represents the logic value 1. The thickness of the silicon dioxide layer is adjusted to obtain the desired operation specifications.
Improvements in the various processes used for fabricating the various types of nonvolatile memory tend to lag improvements in widely used processes such as the advanced CMOS logic process. For example, processes for devices such as flash EEPROM devices tend to use 30% more mask steps than the standard advanced CMOS logic process to produce the various special regions and structures required for the high voltage generation circuits, the triple well, the floating gate, the ONO layers, and the special source and drain junctions typically found in such devices. Accordingly, processes for flash devices tend to be one or two generations behind the standard advance CMOS logic process and about 30% more expensive on a cost-per-wafer basis. As another example, processes for antifuses must be suitable for fabricating various antifuse structures and high voltage circuits, and so also tend to be about one generation behind the standard advanced CMOS process.
The present invention discloses a CMOS compatible single-poly nonvolatile memory cell and array, and the programming circuits and methods associated therewith.